In many integrated circuit devices, it is desirable to provide a system clock, or reference clock, signal to a number of devices within the integrated circuit package. It is also desirable to uniformly delay the reference clock signal such that the clock signal is supplied to the appropriate devices simultaneously. Typically, the clock signal is delayed by the combination of the clock buffers and a clock routing tree, or grid. A known clock buffer is illustrated in FIG. 1.
FIG. 1 is a schematic diagram of a known clock buffer 11. A clock input signal CKIN is supplied on connection 17 to one input of NAND gate 12 and one input of NOR gate 14. NAND gate 12 provides output X on connection 21 and NOR gate 14 provides output Y on connection 19. Outputs X and Y are the inverse of clock input signal on connection 17. NAND gate 12 provides input to transistor 22 and NOR gate 14 provides input to transistor 24. The output of transistors 22 and 24 in the form of a signal Z is provided over connection 26 to both inverter 27 and inverter 29. Inverter 29 supplies signal F over connection 18 to an input of NOR gate 14 and inverter 27 provides the inverse clock signal output NCK on connection 31 as feedback to NAND gate 12 via connection 16 and as input to inverter 28, the output of which is supplied as input to inverters 27 and 29.
The operation of clock buffer 11 is as follows.